claude-hardware-in-the-loop — скилл

---
name: hardware-in-the-loop
description: Sets up and runs the agent-driven hardware-in-the-loop engineering method for a hardware project - generator-first KiCad boards with Freerouting and live part verification, parametric CadQuery CAD with plug-in parts and mass/CG tables, C firmware host-tested against a native C/C++ digital twin (models for rigid bodies, brushed and brushless motors, joints, thermal, batteries, sensors; scenarios over seeds; a C ABI) hosted in Unreal Engine 5.8.4+ or Isaac Sim, CUDA Monte Carlo sweeps, verified research citations, DECISIONS / QUESTIONS records, a PowerShell CI matrix with no-shortcut and portability audits, dev/main branching with merge locks, machine-safety slots, detached jobs, usage-limit handoffs and overnight sessions, in either single-session or swarm mode. Use when the user says "hardware in the loop", "digital twin", "firmware in the loop", "set up a hardware project", "PCB/CAD/firmware swarm", mentions simulating firmware in Unreal or Isaac Sim, asks to scaffold a hardware repo for agents, or wants agents to design boards, enclosures, firmware or a twin with gates.
---

# Hardware in the loop

You are setting up (or running) a hardware project where agents do the engineering and gates prove it. Read this
whole file before acting. This is a starting point the project grows into its own harness, not a finished
product: adapt every template to the project, and say so to the owner when something here does not fit. The method is described in the repository's `docs/` (METHOD, PCB, CAD, FIRMWARE, SIM, SWARM,
TOOLS, LESSONS); this file is the procedure.

## 0. Say the cost first

Before anything else, tell the user, plainly:

> Running this method with a swarm of agents is expensive. On the project it comes from, one swarm day burned 4-5
> million tokens, mostly by waking lane agents that each carried 300-800k tokens of context. Three modes:
> - **chain** (recommended): one long lead session (Fable or Opus) hands bounded cards to one or two subagents at a time
>   (Opus or Sonnet), takes the reports, then goes on. The logs and trial and error stay out of the lead's context.
> - **single**: one session, no subagents, cheapest on small projects.
> - **swarm**: a lead plus parallel lanes, fastest wall-clock, by far the most expensive.
> Which mode do you want? (recommended: chain)

Record the answer as `mode` (`chain`, `single` or `swarm`). A subagent or two on bounded cards is not a swarm: in `chain`
mode that is the normal way to work. Do not run a lead with parallel lanes before the user chose swarm mode.

## 1. Onboarding interview

Run the interview in `references/interview.md` through the question dialog: batches of at most four questions, the
recommended default first in every question. When a question gets no answer, take the default and write
"default taken" next to it. Cover: project goal and definition of done, goals in order, budget, quantities, default
printed material (carbon-fibre nylon / PETG / PLA / machined aluminium), fastening (heat-set inserts / thread-forming /
through-bolts), enclosure (sealed / vented / open), mechanical clearance, PCB fab and assembly vendor, MCU family, main
supply and worst transient, board class and coating, simulation tiers (native twin / Isaac Sim / Unreal) and the GPU,
machine limits (CPU cap default 90 %, RAM kept free for the system default 4 GB, free-disk floor default 50 GB),
archive location, the web CAD viewer (copy it into the project, default yes), usage tripwire (default 95 %), standing decisions.

Then batch 6 (the build spec: environment, temperature range, IP rating and cooling, standards such as IPC class or
MIL-STD-810H / 461G, wire such as SAE AS22759 "Tefzel", EMC, vibration, derating headroom) and batch 7 (how the
owner likes to work: long sims detached in the background at below-normal priority or only overnight, engines only
when they say, how results reach them, what happens to questions while they are away). Also ask:

- the firmware language, recommending C (say why: the same core compiles for the board and the twin; Python stays
  for tools, CAD and the Isaac harness);