Verilog Generator skill
A Verilog-2001 design skill that writes RTL from a brief and explains and repairs existing modules with a check report
- 323 ★ on the repository
- Last commit
- Apache-2.0
Extended access
Why this level
- The skill runs external verification tools and, with remote validation configured, connects over SSH to your server
- When repairing existing RTL it changes project files, and you choose the mode for applying edits
Install
- Works in
In your terminal, with SkillFoxx CLI
npx skillfoxx add skills/verilog-generatorDetects the agents on your machine, shows the access level and pins the version.
Other ways to install
Access and checks
How we reviewExtended accessThe tool runs code or makes network calls and only reads external data.
- The skill runs external verification tools and, with remote validation configured, connects over SSH to your server
- When repairing existing RTL it changes project files, and you choose the mode for applying edits
This is third-party code. Review the repository files before installing.
What it does
Verilog Generator guides an agent through typical digital design tasks in Verilog-2001. The skill creates a module from a clear requirement and explains existing RTL: ports, clocking, reset and state. It also adds semantic comments and repairs a module from compiler, linter or simulator diagnostics. Before generating, the skill shows a preview: the interface with signal widths, reset behavior and at least one cycle-level WaveDrom scenario. Code is written only after you confirm it. If data is missing, the agent asks questions and leaves the interface unguessed. What you receive is a .v file with readable RTL, a same-name Markdown specification and WaveDrom diagrams. A testbench scaffold comes on request. Static review, simulation, synthesis and a hardware result are reported separately, and a check that was not run is never presented as done. It ships with interface templates for AXI, AHB and APB plus ADC and DAC families. For validation in external environments it uses Vivado xsim, or VCS with Verdi or iverilog when xsim is absent. Remote runs go through a server you configure.
Who it is for. For FPGA and ASIC engineers, students and teachers who write and verify Verilog-2001 RTL together with Codex, Claude Code or Gemini CLI.
Good fit when
- You need a new module, such as an AXI-Stream packet counter, with a behavior preview before code is generated
- You need to understand someone else's RTL and find synthesis risks without changing the file
- You want semantic comments added to a Verilog file and proof that only comments changed
- A module fails in the simulator and you want a proposed fix and validation results from the attached log
- You need module specifications and WaveDrom diagrams beside the sources
Not a fit when
- The project is SystemVerilog or VHDL: the skill targets synthesizable Verilog-2001
- You want a hardware or post-synthesis result without access to Vivado or other tools: without external evidence the skill gives only static review
- You want a one-off module stub with no documentation: the skill outputs a specification with every created or modified module
- You need a one-character fix and strict profile checks are overkill
Example request
Use $readable-verilog-generator to create a Verilog-2001 AXI-Stream packet counter. First ask about the interface and show the specification and WaveDrom preview before generating code.Limitations
Since version 2.0.0 the skill installs through the install.ps1, install.sh or install.bat scripts of the release package. Codex, Claude, Gemini and DeepSeek are supported. Before writing, the script backs up an existing target, and the `--dry-run` flag writes nothing. Before work the skill checks dependencies and asks permission to install anything missing.
Remote validation needs your own server configured in the .settings/verilog.remote.json file. The skill is strict: generated code passes a gate on naming, comments and structure with zero errors.
How to disable. Delete the skill folder from your agent's skills directory. When installed through the scripts, the previous version is kept as a backup that you can restore by hand.
FAQ
How do I install Verilog Generator in Codex or Claude Code?
Ask the agent to install the skill from https://github.com/Eriemon/verilog-generator. Manually: in the release package run `./install.sh --platform codex --dry-run --json`, then repeat without `--dry-run`. For Claude use `--platform claude`.
How do I call the skill after installing?
In the same conversation write `$readable-verilog-generator` or describe a Verilog task in plain words. In the request it helps to ask for the specification and a WaveDrom preview before RTL is generated.
How does a module review differ from a repair?
A review only reads the RTL and reports on eight gates without changing anything. A repair binds to real code, reproduces the issue and applies the smallest fix. You choose how edits are applied: conservative, semi-automatic or automatic.
Does comment mode change a module's logic?
No. The skill keeps a normalized baseline, edits only // comments and compares the RTL tokens with the baseline. The final gate then runs again.
Which simulators does the skill use?
Vivado xsim is preferred, then VCS with Verdi, then iverilog with vvp. Yosys gives evidence of implementation readiness only.
Discussion
No questions or reviews yet.
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Comparison with similar tools
Entries that share the main search query, and how they differ.
| Entry | Official | Authentication | Repository stars | Main difference |
|---|---|---|---|---|
| Verilog Generator (this entry) | no | 323 | ||
| Embedded Skills | no | 773 | skills for embedded development: compilers, debuggers and buses, from code to hardware checks | |
| altium-designer-mcp | no | not required | 86 | an MCP server for Altium Designer libraries, footprints and symbols, covering circuit boards |
README in short
The description explains what to prepare for each task and gives four ready requests. It ends with an AXI-Stream counter example with a static check.
README badge
Original SKILL.md
--- name: readable-verilog-generator description: >- Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed repair, and workflow trace diagnosis. --- # Readable Verilog Generator Generate, analyze, improve, and verify readable Verilog-2001 RTL through the bundled runtime under `scripts/python/`. Keep design RTL and verification testbenches in `.v` files, use `scripts/python/facade/verilog_api.py` for host integration, and treat formatter-AST and external-tool evidence as stronger than model self-assessment. ## Route - `create/write`: confirm the design contract, then use `requirements -> codegen_plan -> spec_document -> python -> rtl`. - `deep_review`: insert a non-empty structured review between the Python semantic model and RTL; it must cover interface, reset, timing/pipeline, handshake or FSM behavior, width, synthesis, testbench coverage, and risks. - `review/analyze`: remain read-only and report the eight public gate states before suggesting changes. - `annotate`: preserve an immutable normalized baseline, change only `//` comments, prove token equivalence from that baseline, and rerun the final deliverable gate. - `repair/refactor`: bind the task to real RTL, reproduce or validate the issue, and apply the smallest evidence-backed change. - `agentic_repair`: use the existing-RTL `verify_existing_verilog(...)` loop with an explicit `conservative`, `semi_auto`, or `auto_apply` choice. - `validate`: collect static or external evidence without implicitly editing RTL. - Load `references/workflows/verilog_dispatcher.md` before routing. Existing assets, logs, waveform clues, and mixed inputs use its read-only entry decision before any generation, validation, backup, or remote action. ## Install v2.0.0 The package root contains `install.ps1`, `install.sh`, and `install.bat` beside this `SKILL.md`. They share the package-local Python backend and read only the generated installer projection under `assets/installer/` plus the same-level bootstrap descriptor. Platform IDs, root resolution, target templates, status text, exit codes, transaction policy, and verification cases are data-driven by `config/installer/`; do not add platform branches or current test values to code or comments. Install only from a versioned payload with the configured `RELEASE_RECEIPT.json`. Use `--DryRun`/`--dry-run` to validate without creating transaction resources; use replacement flags only when the target and overwrite intent are explicit. A transaction handles one platform and one target, preserves unlisted target files, writes an install receipt, and attempts rollback on failure. Unknown IDs and source directories without a valid release receipt fail closed. See `references/skill/installation.md` for the complete contract and parameterized invocation templates. ## Generate And Modify