SoC Agent Skills
Three skills with MCP for SoC design: a Verilog top, CRG workbooks and WaveDrom timing diagrams.
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Why this level
- Skills run local MCP servers and scripts that read Verilog sources and write generated files.
Install
- Works in
In your terminal, with SkillFoxx CLI
npx skillfoxx add skills/soc-agent-skillsDetects the agents on your machine, shows the access level and pins the version.
Other ways to install
Access and checks
How we reviewExtended accessThe tool runs code or makes network calls and only reads external data.
- Skills run local MCP servers and scripts that read Verilog sources and write generated files.
This is third-party code. Review the repository files before installing.
What it does
The repository combines three skills for system-on-chip design, each with its own stdio MCP server. `soc-integrate` extracts ANSI-style submodule ports, stitches a Verilog top from them, snapshots interfaces and refreshes the top with `soc_update` only when submodule ports changed. `crg-design-gen` turns a requirement table into CRG design workbooks and clock and reset trees. `wavedrom-gen` converts a natural-language description into official WaveDrom JSON5 and outputs SVG, PNG or HTML. It also installs as a Cursor plugin. Each folder is standalone: `SKILL.md` is the agent contract, with an MCP server, scripts and tests beside it. The set has no combined build system.
Who it is for. Digital and SoC design engineers who want to hand an agent the routine: top-level assembly, clocking schemes and signal diagrams.
Good fit when
- A chip top module must be built or refreshed from submodule ports.
- A clocking requirement table must become a CRG workbook with clock and reset trees.
- A protocol described in words must become a WaveDrom timing diagram.
- Submodule ports did not change and a snapshot and CSV suffice without regeneration.
Not a fit when
- You need a full SoC build system: `soc-build` lives elsewhere.
- You do not work with Verilog or WaveDrom.
- Local MCP servers on Python and Node.js cannot be run.
Example request
Build the chip top module from these submodules and save an interface snapshot.Limitations
The set does not replace a SoC build system: the authors state that `soc-build` lives elsewhere. `wavedrom-gen` needs Node.js 20 or newer, and for PNG run `npm ci --omit=dev` because `node_modules` is not committed and `@resvg/resvg-js` installs a platform-specific native binary. The MCP-enabled skills run over stdio. The Cursor build is copied to `~/.cursor/plugins/local` and the window reloaded. `mcp.json` uses `${CURSOR_PLUGIN_ROOT}`; for a strictly spec-conformant client replace it with `${PLUGIN_ROOT}`. Check generated output with your synthesis tools.
How to disable. Remove a skill with `npx skills remove` or delete its folder, and for Cursor delete the plugin folder in `~/.cursor/plugins/local`.
FAQ
How do I install a single skill?
Run `npx skills add siliconpeasant/soc_agent_skill --skill soc-integrate -g`. Without `-g` it installs into the project and `-a` picks a client.
What is in the set?
Three skills: `soc-integrate`, `crg-design-gen` and `wavedrom-gen`. Each has its own MCP server.
When is soc_update needed?
Only when the listed submodules' ports changed. With unchanged ports a snapshot and CSV are enough and no regeneration is needed.
What does wavedrom-gen output?
Official WaveDrom JSON5 plus SVG, PNG or HTML output.
How do I install it in Cursor?
Copy the `wavedrom-gen` folder to `~/.cursor/plugins/local/wavedrom-gen`, run `npm ci --omit=dev` in its `skills/wavedrom-gen` and reload the window.
Discussion
No questions or reviews yet.
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README in short
The README table lists each skill's purpose, stdio MCP availability and a `SKILL.md` link. Skills have no separate README and the agent contract lives wholly in `SKILL.md`.
README badge
Original SKILL.md
---
name: soc-integrate
description: >
Extract RTL ports, generate instances/wrappers/top modules, and track
interface changes through snapshots and integration configs. Use for
generated SoC top-level integration and port-change maintenance.
soc_update only after listed submodule ports change; do not regenerate a
top just to close a delivery stage.
---
# SoC Integrate (`soc-integrate`)
Generate and maintain a **chip/subsystem top** from Verilog submodule files.
Do not hand-edit generated instances. Keep connection intent in a port-map JSON.
Prefer the bundled MCP server. CLI is available for local use and tests.
## MCP tools
| Tool | Purpose |
|---|---|
| `soc_extract` | Parse ANSI module ports |
| `soc_instantiate` | Emit `.port(signal)` instance |
| `soc_wrap` | Pass-through wrapper |
| `soc_csv` | Port CSV |
| `soc_snapshot` / `soc_diff` | Port snapshot and delta |
| `soc_integrate` | Stitch modules into a generated top + `.integrate.json` |
| `soc_extract_map` | Recover mappings from an existing top |
| `soc_update` | Refresh that top after **listed submodule ports change** |
| `soc_remove` | Drop a module from the config and refresh |
Register stdio:
```json
{
"mcpServers": {
"soc-integrate": {
"command": "python3",
"args": ["/path/to/soc-integrate/mcp_server.py"]
}