GateFlow plugin
A Claude Code plugin that writes, lints, simulates and formally verifies SystemVerilog, Verilog and VHDL for FPGA boards.
- 119 ★ on the repository
- Last commit
Extended access
Why this level
- The plugin runs external synthesis and simulation programs in the project directory.
Install
- Works in
In your terminal, with SkillFoxx CLI
npx skillfoxx add plugins/gateflowDetects the agents on your machine, shows the access level and pins the version.
Other ways to install
Access and checks
How we reviewExtended accessThe tool runs code or makes network calls and only reads external data.
- The plugin runs external synthesis and simulation programs in the project directory.
This is third-party code. Review the repository files before installing.
What it does
GateFlow adds skills, agents and commands for digital design to Claude Code. From a natural-language description and a board name the plugin generates RTL, then runs Verilator checks, simulation and Yosys synthesis. For formal verification it writes SVA properties and configures SymbiYosys. The synthesis report lists LUT, flip-flop, BRAM and DSP usage, and board targets get a constraints file with pin assignments. It includes agents for code generation, auditing and board design, and skills trigger automatically from request context. Commands such as `/gf-formal` and `/gf-synth` run individual stages. Tools such as Verilator, Yosys, SymbiYosys and nextpnr are installed separately, and some are optional. The README also covers compatibility with other agents: Codex, Cursor, Copilot, Cline and Windsurf.
Who it is for. FPGA engineers and students who write RTL and want verified code for a specific board.
Good fit when
- An SPI controller is needed for an Arty A7 board with a constraints file.
- A FIFO is proven formally so that overflow is excluded by an SVA property.
- After synthesis, LUT, flip-flop and BRAM usage is reviewed.
- An existing SystemVerilog module goes through audit and lint.
Not a fit when
- The flow targets ASICs in closed commercial EDA suites.
- Verilator and Yosys cannot be installed on the workstation.
- The BSL-1.1 license does not fit commercial distribution.
Example request
Write an SPI controller for Arty A7, run Verilator lint and simulation, then show the synthesis report for LUTs and flip-flops.Limitations
The plugin calls external programs that must be installed separately: Verilator, Yosys, SymbiYosys, nextpnr. Without them code generation works but verification and synthesis do not. The repository uses the BSL-1.1 license (Business Source License), which limits commercial use. Auto-activating skills trigger on request context, so disable the plugin for unrelated work. Support for Codex, Cursor and other agents goes through separate compatibility files. The last commit dates from September 2026.
How to disable. Run `claude plugin uninstall gateflow` and remove the marketplace with `claude plugin marketplace remove` if needed. Generated RTL files stay in your project.
FAQ
Which tools must be installed separately?
Verilator is recommended for lint and simulation. Synthesis needs Yosys, formal checks need SymbiYosys and place-and-route needs nextpnr.
How do I start formal verification?
The `/gf-formal` command or a request like "prove the FIFO never overflows" writes SVA properties, configures SymbiYosys and runs the proof.
What does the synthesis report show?
Used LUTs, flip-flops, BRAM and DSP blocks. The `/gf-synth` command runs Yosys and prints these figures.
Does the plugin work with Codex and Cursor?
Yes, through compatibility files in the repository. The README section on cross-tool compatibility gives the steps.
Can the plugin be used in a commercial project?
BSL-1.1 sets the terms: read the `LICENSE` file before using it in a commercial product.
Discussion
No questions or reviews yet.
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README in short
The README covers a quick start, skills, agents and commands, board setup and updates. A separate section explains use with other tools.