VeriFlow-CC skill
The vf-rtl skill drives Claude Code through four RTL design stages: from spec and code to simulation and Yosys synthesis.
- 55 ★ on the repository
- Last commit
Extended access
Why this level
- The installer writes files into `~/.claude/` and the agent runs simulators and Python scripts on your machine.
Install
- Works in
In your terminal, with SkillFoxx CLI
npx skillfoxx add skills/veriflow-ccDetects the agents on your machine, shows the access level and pins the version.
Other ways to install
Access and checks
How we reviewExtended accessThe tool runs code or makes network calls and only reads external data.
- The installer writes files into `~/.claude/` and the agent runs simulators and Python scripts on your machine.
This is third-party code. Review the repository files before installing.
What it does
VeriFlow-CC is a skill with a set of subagents for digital circuit design in Verilog. `/vf-rtl <project folder>` starts a four-stage pipeline: a specification with a golden model, per-module RTL generation, simulation with error recovery, and linting with synthesis. The main Claude Code session controls transitions while separate subagents write code and tests, lint and synthesize. State is saved to JSON so the pipeline resumes after a session restart. Simulation runs on `iverilog` and `cocotb`, synthesis and equivalence checking on `yosys`. No Python dependencies need installing: the scripts ship with the project.
Who it is for. Digital design engineers and students who describe a block's requirements in a file and want verified Verilog from an agent.
Good fit when
- A `requirement.md` file describes the block and you want RTL and tests from a single run.
- Simulation fails and the agent must analyse waveforms with a budget of three fix attempts.
- Before handing in, lint and Yosys synthesis must run and produce a report.
- Work on a block spans several days and the pipeline must resume where it stopped.
Not a fit when
- The project is VHDL or SystemVerilog without Verilog subagents: the skill targets Verilog.
- A full physical design flow down to chip layout is needed.
- `iverilog` and `yosys` cannot be installed on the machine.
Example request
/vf-rtl /path/to/my_alu: run all four stages and show the synthesis report.Limitations
Installation is from source: `python install.py` copies the skill and subagents into `~/.claude/`, and `python install.py --uninstall` removes them. The EDA tools `iverilog`, `vvp` and `yosys` must be installed separately: the skill locates them at step zero. The pipeline targets Claude Code. A `requirement.md` file is mandatory input, other files are optional. The last commit was in October 2026.
How to disable. Run `python install.py --uninstall` from the repository clone. Project folders with `.veriflow/` and logs are deleted by hand.
FAQ
Which input files are needed?
`requirement.md` with the block's functions is mandatory. Constraints, architecture intent and references go in `constraints.md`, `design_intent.md` and `context/`.
What does the pipeline do?
Four stages: spec and golden model, RTL generation, simulation with fixes, lint and synthesis. Results land in `rtl/`, `logs/` and a synthesis report.
What if the pipeline is interrupted?
State is stored in JSON. Running `/vf-rtl` again in the same folder continues from the last stage.
Do I install Python libraries?
No, the README describes the skill as dependency-free. Only the EDA tools `iverilog` and `yosys` are needed.
Can I run a benchmark?
Yes, the `--benchmark` flag runs `benchmark_runner.py` after the pipeline and writes a JSON report to `logs/benchmark_report.json`.
Discussion
No questions or reviews yet.
Related
SkillsA Claude Code plugin that writes, lints, simulates and formally verifies SystemVerilog, Verilog and VHDL for FPGA boards.
A Verilog-2001 design skill that writes RTL from a brief and explains and repairs existing modules with a check report
A Claude Code skill for designing PCBs, CAD and firmware as code that writes fab files only after every gate passes
Claude Code project template: spec, design, code and deploy live in the repo, and ten skills guide the agent by phase.
A Claude Code plugin with a plan, execute, verify, hand off pipeline, memory across sessions and 51 commands.
Three Claude Code plugins: the savvy-flow orchestrator with tiered subagents and two mods for a progress panel and a cache timer
README in short
Describes the four-stage architecture, source installation, input file format, constraints and the Yosys equivalence check.